IC tray or logistics tray: which does your workflow need?

An IC tray presents chips to machines; a logistics tray moves loads across a facility. The two families share the same category page and the words “anti-static tray,” yet they differ by three orders of magnitude in scale. Map the workflow first, then read each published table on its own terms before writing either RFQ.

Both families appear on the ESD Tray category page. For board-level staging between those two extremes, the PCB tray overview covers the middle ground.

Part 1. Separate the two jobs behind one category

In semiconductor back-end plants, the IC tray is part of the machine interface. Chips sit in a matrix of pockets so handlers, testers, and pick-and-place heads can find every unit in a known position; trays stack into magazines and travel through bake, test, and assembly steps. Format discipline is the whole point.

A logistics tray solves a facility problem instead. Pallet-scale loads — cartons, totes, stacked boxes of finished boards — need a static-safe deck that forklifts and pallet jacks can move without adding charge risk to the material on top. Nobody expects a chip pocket; everybody expects load stability.

Confusion starts when an RFQ says “ESD tray for our new line” without saying which world it lives in. The price, tooling, and evidence questions have almost nothing in common, so the workflow decides before any table is read.

Part 2. Map the workflow before the tray

Write the route down at the scale it really runs. For a chip flow, that means the package method and body size, the process steps the tray passes through (including any bake), the machines that grip or index the tray, and how trays stack and travel between steps.

For a facility flow, record the load per trip, the footprint the racking and trucks expect, whether trays meet automated conveyors, and which zones enforce static control. The line-side staging guide helps place bench-level staging, which is a third job and belongs to neither family here.

One route can contain both worlds: chips leave test in IC trays, get boxed, and the boxes cross the warehouse on a logistics tray. Mapping the handoff points keeps each RFQ scoped to its own leg.

Part 3. Read the published IC tray evidence

The published Sanwei IC Tray product page states that the trays comply with JEDEC international standards and lists package methods including BGA, QFN, QFP, PGA, TSOP, TQFP, LQFP, PLCC, SOC, and SiP. Published rows cover BGA and QFN formats with model designations, matrix counts, temperature, resistance, and weight.

Concrete row examples: the BGA6x8 row records a 16×30 matrix of 480 units, and the QFN5x5 row records 14×35 for 490 units. Listed rows show a temperature MAX of 150 and a surface resistance of 10^5 to 10^11 Ω, with one QFN row showing 10^4 to 10^11 Ω.

The page also explains why those figures exist: chips must be baked before terminal assembly, pins need dimensional stability, and materials should have low water absorption and support reuse. Read every value as row-specific evidence to confirm for the quoted format, not as a family-wide guarantee.

Part 4. Study the published logistics tray evidence

The published Sanwei Anti-static Logistics Tray page works at facility scale. Its table lists three footprints — 1200×1200 mm, 1200×1000 mm, and 1200×800 mm — and two carrying figures: 800 kg active carrying and 2000 kg stable carrying.

Electrical behavior is published as a surface resistance of 1×10^6 to 1×10^9 Ω. The page also names three deck types — Chuan Shape, Nine Angle, and Tian Shape — and notes that further variants can be supplied on request, which is a quotation conversation rather than a published specification.

Match those figures to the mapped route: the footprint against racking and truck forks, the active figure against moving loads, the stable figure against static stacking, and the resistance range against the zone’s program requirement.

Part 5. Compare the families on workflow factors

Set the two published tables side by side and the confusion disappears: the families overlap only in the words “anti-static” and “tray.”

Substitution fails at the interface. A logistics deck cannot present pins to a handler, and no stack of chip trays should meet a forklift. Where a route needs both, specify the handoff — who transfers material, in what container, at which point — instead of forcing one family across the line.

Boards in process sit between the scales: they usually belong in bench trays, magazines, or totes rather than either family here. Keep that middle layer out of both RFQs unless the route genuinely reaches pallet scale.

Part 6. Confirm ESD, bake, and load boundaries

Electrical ranges on both pages are starting points. The buyer’s program defines the requirement, the test method, the measurement conditions, and the evidence format for the specific quoted item — ESD Association standards information frames that program context without approving any carrier.

Thermal and mechanical figures follow the same rule. A temperature MAX of 150 on listed IC tray rows is checked against the documented bake profile for the quoted format, and the 800 kg and 2000 kg carrying figures are reviewed against the actual load, truck, and racking state; neither transfers to the other family, and neither replaces a route trial.

For chip formats, JEDEC standards documents provide the format vocabulary an RFQ can reference. Price, MOQ, lead time, custom footprints, and unlisted formats remain quotation items on both sides.

Part 7. Build the RFQ and sample plan

Split the request by family and attach the workflow map. A clean RFQ names the leg of the route it covers, the published row or type it starts from, and the evidence it needs back.

Product recommendation

For chip presentation in packaging and test, start from the Sanwei IC Tray product page and confirm the quoted format, matrix, temperature, and resistance evidence for the selected row. For facility movement, start from the Anti-static Logistics Tray page and its published footprints and carrying figures.

Send the workflow map through Contact Sanwei to route each leg to the right family and quotation.

Fit Boundary

FAQ

What is an IC tray used for?

It presents packaged chips in matrix pockets for semiconductor packaging and test, so handlers and operators work with known positions. Sanwei’s page states JEDEC compliance and lists supported package methods.

What is an anti-static logistics tray?

A pallet-scale static-safe carrier for facility movement. The published page lists 1200×1200, 1200×1000, and 1200×800 mm sizes, 800 kg active and 2000 kg stable carrying, and a 1×10^6 to 1×10^9 Ω surface resistance.

Can an IC tray and a logistics tray replace each other?

No. One presents chips to machines; the other carries floor-level loads. Substitution fails at the equipment interface, so map the route and specify each leg separately.

Does Sanwei publish IC tray temperature and resistance data?

Yes. Listed rows record a temperature MAX of 150 and surface resistance of 10^5 to 10^11 Ω, with one QFN row showing 10^4 to 10^11 Ω. Values are row-specific and confirmed at quotation.

What sizes does the published logistics tray list?

Three footprints: 1200×1200 mm, 1200×1000 mm, and 1200×800 mm, in Chuan Shape, Nine Angle, and Tian Shape types, with variants handled as quotation requests.

Which tray fits PCB handling between process steps?

Usually neither: boards in process belong in bench-scale trays, magazines, or totes. Reserve IC trays for packaged chips and logistics trays for pallet-scale movement.

What ESD evidence should be requested for either tray?

The electrical target, test method, conditions, measurement locations, and evidence format required by the buyer’s program for the specific quoted row or type.

What should be checked on samples before rollout?

IC side: handler indexing, stacking, and a bake check against the documented profile. Logistics side: load, movement, racking, and zone checks. Both against written acceptance criteria.

References

• ESD Association — standards information
• JEDEC — standards documents